The increasing need to form planar surfaces in semiconductor device fabrication has led to the development of process technology known as chemical-mechanical-polishing (CMP). In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of an abrasive slurry. Most commonly, the layer to be planarized is an electrically insulating layer overlying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
A common requirement of all CMP processes is that the substrate be uniformly polished. In the case of polishing an electrically insulating layer, it is desirable to polish the layer uniformly from edge to edge on the substrate. To ensure that a planar surface is obtained, the electrically insulating layer must be uniformly removed. Uniform polishing can be difficult because several machine parameters can interact to create non-uniformity in the polishing process. For example, in the case of CMP, misalignment of the polishing wheel with respect to the platen can create regions of non-uniform polishing across the diameter of the platen. Other machine parameters, such as non-homogeneous slurry compositions, and variations in the platen pressure, and the like, can also create non-uniform polishing conditions.
Recently, CMP has been applied to the fabrication of trench isolation regions in metal-oxide-semiconductor (MOS) devices and bipolar-complementary-MOS (BiCMOS) devices. The isolation process typically includes the formation of trenches in a silicon substrate, followed by the deposition of silicon dioxide over the surface of the substrate and into the trenches. The silicon dioxide is then polished back by CMP. A polish stop layer is provided on the substrate surface to prevent the unwanted removal of underlying portions of the substrate. The silicon dioxide is ground away by the polish wheel until the polish stop layer is reached. Ideally, upon exposure of the polish stop layer, the polish removal ceases resulting in a uniformly smooth surface across the entire substrate. Important measures of the CMP process are the edge-to-edge polishing uniformity, known as global uniformity, and local uniformity. The local polishing uniformity is influenced by the material characteristics of individual regions of the substrate surface.
In a trench isolation process, local nonuniformity in a CMP process can depend upon the pattern density of isolation regions in the semiconductor substrate. Variations in pattern density can lead to variations in the polishing characteristics of the substrate within individual die in the substrate. Typically, the amount of material removed in a given amount of time depends upon the pattern density of isolation regions. For example, localized areas of nonuniform polishing can occur in substrate areas having varying degrees of pattern density. Areas having closely spaced active devices are prone to slower, but uniform, polishing due to the presence of adequate polish stop material underlying the layer being planarized. Correspondingly, in areas having a low pattern density, a smaller area of exposed polish stop material is present, and more material is removed from the substrate. Moreover, large areas of exposed planarizing material are susceptible to dishing. Localized nonuniform polishing characteristics are illustrated in FIGS. 1-a and 1-b.
FIG. 1-a illustrates, in cross-section, a portion of a semiconductor substrate 10 formed in accordance with a CMP process of the prior art. The substrate includes a plurality of high-density isolation regions 12. Isolation regions, such as those illustrated, are typically employed to isolate portions of an integrated circuit device. The isolation regions are formed in a semiconductor substrate and placed in close proximity to each other. FIG. 1-a shows a portion of substrate 10 following the planarization of the substrate. A polish stop layer 13 overlies a surface 14 of substrate 10.
FIG. 1-b illustrates, in cross-section, a portion of semiconductor substrate 10 having low-density active regions surrounded by wide isolation regions 16 formed therein. The portion of substrate 10 illustrated in FIG. 1-b is planarized by the same process used to form substrate surface 14, and surface 14 is continuous with that shown in FIG. 1-a. By comparing FIGS. 1-a and 1-b, it is seen that, following the planarization process, high-density isolation regions 12 protrude above substrate surface 14, while wide isolation regions 16 have been "dished" by the polishing process, and are recessed below substrate surface 14.
As shown in FIG. 1-a, the CMP process forms substrate surface 14 below the uppermost surface of isolation regions 12. The condition illustrated in FIG. 1-a is created by the larger quantity of polish stop material in the densely packed region of the substrate. Subsequent processing steps, which remove the polish stop layer 13 formed on the surface of substrate 10 prior to the CMP process, tend to equalize the substrate surface 14 and the uppermost surface of isolation regions 12.
In regions of the substrate containing large isolation regions, and correspondingly less polish stop material, the situation illustrated in FIG. 1-a is reversed. The initial planarization process results in removal of substantial quantities of dielectric material. In substrate regions such as that shown in FIG. 1-b, the polish stop layer 13 is reduced to a very thin layer by the polishing process. The polishing process has dished out the isolation regions 16 reducing their total thickness. The nonuniform polishing thus reduces the total thickness of isolation regions 16 as compared to isolation regions 12. The problem is exacerbated by subsequent processing steps following planarization, where the surface of 16 can be recessed below the surface 14, leading to the formation of corner regions 18.
Although the non-uniform planarization process is itself a serious detriment to high quality integrated circuit fabrication, the situation illustrated in FIG. 1-b creates a special problem, which impacts the performance of transistor devices in an integrated circuit. The non-uniform planarization results in the formation of corner regions 18, illustrated in FIG. 1-b. Corner regions 18 are detrimental to the operation of MOS transistors formed in portions of the substrate intermediate to isolation regions 16.
FIG. 1-c illustrates, in cross-section, an MOS transistor 20 fabricated in a region of substrate 10 between isolation regions 16. MOS transistor 20 includes a gate electrode 22 separated from substrate 10 by a gate dielectric layer 24. Portions of gate electrode 22 and gate dielectric layer 24 necessarily overlie corner regions 18. The presence of corner regions 18 in MOS transistor 20 can cause sub-threshold leakage currents in the channel region of the transistor during periods when the transistor is switched off.
The non-uniform planarization associated with varying densities of isolation regions affects a wide variety of integrated circuit devices. Virtually all MOS and BiCMOS integrated circuits include regions of varying isolation geometry and packing densities. Accordingly, improved planarization techniques are necessary to overcome both global and localized non-uniform planarization induced by variations in the pattern-density of isolation regions.